1. Field of the Invention
The present invention relates to a successive approximation analog-to-digital converter (ADC), especially to a charge-redistribution successive approximation ADC and a control method thereof.
2. Description of Related Art
FIG. 1 shows a block diagram of a conventional charge-redistribution successive approximation analog-to-digital converter (ADC). In one operation cycle (including a capacitor switching phase and a voltage comparison phase) of the charge-redistribution successive approximation ADC, the successive approximation register (SAR) 120 determines the value (1/0) of one of the bits of a digital output code Dn according to a comparison result of the comparator 105, and the control circuit 130 then generates a control signal Csw according to the digital output code Dn (i.e., indirectly based on the comparison result). Next, the digital-to-analog converter (DAC) 110, according to a switching status of an internal capacitor array changed by the control signal Csw (controlling one of the ends of the capacitor to be grounded or coupled to a reference signal Vref generated by the reference signal generating unit 140), causes the charge on the capacitors to be redistributed, in a way that the level of an inverted input end or non-inverted input end of the comparator 105 is changed to further change the comparison target of a next operation cycle of the successive approximation ADC. By repeating the above steps, the bits of the digital output code Dn are sequentially determined from the most significant bit (MSB) towards the least significant bit (LSB), and the value representing the digital output code Dn gradually approximates the input signal vi during such process.
The circuit in FIG. 1 may be applied to differential signals, or single-ended signals (each formed by one data signal and one common mode signal). As the comparator 105 is non-ideal, its input offset voltage is severely affected by the common mode signal of the input signal vi. For example, in certain circumstances, when the common mode signal of the input signal vi changes by 250 mV, the input offset voltage of the comparator 105 may become as much as 1.8 mV, hence aggravating the total harmonic distortion (THD) of the successive approximation ADC as well as reducing the accuracy of the successive approximation ADC. The publication “A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS” (Yan Zhu, et al., “A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1111-1121, June 2010), provides a solution that utilizes one half of the positive voltage VDD as an additional reference voltage. However, the positive voltage VDD may get lower with the development of the manufacture process. Thus, the above publication encounters an issue of being not easily conducted due to an inadequately low reference voltage in an advanced manufacture process, resulting in implementation difficulties.